Reference is now made to FIG. 1 which illustrates a circuit diagram of a conventional low-to-high level shifting circuit 10 known to those skilled in the art. The circuit 10 employs an input stage 12 in the form of a differential amplifier which receives a complementary input signal IN/INB at a logic levels referenced to lower voltage supply domain (for example, with logic high at 1V and logic low at ground).
The amplifier includes a first circuit leg formed by series connected transistors 14, 16 and 18, wherein transistor 14 is a p-channel MOSFET and transistors 16 and 18 are n-channel MOSFETs. The source of transistor 14 is coupled to a positive supply node AVDD which receives a higher supply voltage (for example, referenced to a higher voltage supply domain with 5V equal to logic high). The drain of transistor 14 is coupled to the drain of transistor 16. The source of transistor 16 is coupled to the drain of transistor 18, and the source of transistor 18 is coupled to a negative supply node (ground) GND. The gate of transistor 16 is coupled to receive the input signal IN (which, as discussed above, has logic levels referenced to the lower voltage supply domain that is less than the high voltage supply domain at node AVDD). The gate of transistor 18 receives an input signal OUTDIFFB (wherein this signal OUTDIFFB is a feedback signal to be described in more detail below).
The amplifier includes a second circuit leg formed by series connected transistors 24, 26 and 28, wherein transistor 24 is a p-channel MOSFET and transistors 26 and 28 are n-channel MOSFETs. The source of transistor 24 is coupled to the positive supply node AVDD, and the drain of transistor 24 is coupled to the drain of transistor 26. The source of transistor 26 is coupled to the drain of transistor 28, and the source of transistor 28 is coupled to the negative supply node (ground) GND. The gate of transistor 26 is coupled to receive an input signal INB, (which is the complement of signal IN and has logic levels also referenced to the lower voltage supply domain that is less than the higher voltage domain at node AVDD). The gate of transistor 28 receives an input signal EN. In an embodiment, the signal EN is configured as an enable control signal operable to control enabling of circuit 10 operation (i.e., it is an enable signal referenced to the higher voltage supply domain). Alternatively, the gate of transistor 28 is connected to node AVDD.
The gates of transistors 14 and 24 are coupled together and to the drain of transistor 14. Thus, transistors 14 and 24 are connected as a current mirror.
The output of the differential amplifier input stage 12 is taken from the coupled drain nodes of transistors 24 and 26 as a level shifted signal OUTDIFF.
A first CMOS inverter circuit 30 has an input coupled to receive the signal OUTDIFF, and an output generating the feedback signal OUTDIFFB. A second CMOS inverter circuit 32 has an input coupled to receive the signal OUTDIFFB, and an output generating an output signal OUT. The first and second CMOS inverter circuits 30 and 32 are coupled between the positive supply node AVDD and the negative supply node (ground) GND. The output signal OUT (with logic levels referenced to the higher supply voltage domain) is a level shifted up version of the input signal IN (with logic levels referenced to the lower voltage supply domain), for example, level shifting from 1V logic to 5V logic.
The circuit 10 further includes a first pull-up transistor 40 of the p-channel MOSFET type whose source is coupled to the positive supply node AVDD and whose drain is coupled to the output of the differential amplifier input stage 12 (at the coupled drain nodes of transistors 24 and 26 and referenced as signal OUTDIFF). The gate of transistor 40 is coupled to receive the input signal EN (wherein this signal EN is configured as an enable control signal operable to control enabling of circuit 10 operation).
The circuit 10 still further includes a second pull-up transistor 42 of the p-channel MOSFET type whose source is coupled to the positive supply node AVDD and whose drain is coupled to the output of the differential amplifier input stage 12 (at the coupled drain nodes of transistors 24 and 26 and referenced as signal OUTDIFF). The gate of transistor 42 is coupled to the output of the first CMOS inverter circuit 30 and is thus controlled by the signal OUTDIFFB. The pull-up transistor 42 coupled in the circuit 10 as described forms a feedback path.
The feedback path through transistor 42 is required in the circuit 10 in order ensure that the output of the differential amplifier input stage 12 (signal OUTDIFF) is properly pulled up to the voltage at the positive supply node AVDD when the low voltage input signal IN switches from logic low to logic high. In this regard, those skilled in the art understand that transistor 24 is not capable of pulling up the output of the differential amplifier input stage 12 (signal OUTDIFF) to the voltage at the positive supply node AVDD by itself. The transistor 24 is instead capable of pull-up only to an intermediate voltage equal to the voltage at the positive supply node AVDD minus the threshold voltage (vtp24) of transistor 24 (AVDD−vtp24).
An incomplete pull-up of the output of the differential amplifier input stage 12 (signal OUTDIFF) is not desirable because a) large currents will flow in the first and second CMOS inverter circuits 30 and 32, and b) an extended time may be needed for switching the output signal OUT from low-to-high logic level or operational failure may occur where the output signal OUT does not switch logic states at all. The feedback path through transistor 42 addresses the foregoing concerns by providing a pull-up circuit, activated by the signal OUTDIFFB in the logic low state, operable to bring the logic high level OUTDIFF signal fully to the voltage at the positive supply node AVDD.
In order to ensure that the circuit 10 functions properly, the feedback path through transistor 42 must be properly designed. Specifically, the transistor 42, operable as a pull-up path, must be designed to be “weaker” than the pull-down path provided in the second leg of the differential amplifier input stage 12 through n-channel transistors 26 and 28. This is required so that transistor 26, when activated by a logic high level for signal INB, can successfully pull the output of the differential amplifier input stage 12 (signal OUTDIFF) to logic low (ground).
It is difficult to ensure the required strength relationship between the pull-up path and pull-down path across all process (P), voltage (V) and temperature (T) corners. Still further, this task becomes even more difficult with increased differences between the lower voltage supply domain of the input signals IN/INB and the higher voltage supply domain at the positive supply node AVDD (for example, 1V reference for signals IN/INB and AVDD=5V). To ensure full functionality across all PVT corners, those skilled in the art have designed the transistor 42 of the pull-up feedback path to be excessively weak in that the transistor 42 is sized such that its best case strength across the PVT corners is weaker than the worst case strength of the pull-down transistors 26 and 28. However, this design methodology is recognized by those skilled in the art to be overly pessimistic, and circuits 10 designed in this manner tend to operate with an excessively large skew in rise time and fall time and with increased DC current consumption.
Those skilled in the art have further noted, because the transistor 42 of the pull-up feedback path is of the p-channel type and the transistors 26 and 28 of the pull-down path are of the n-channel type, that satisfying the required strength relationship between the pull-up path and pull-down path across all PVT corners becomes even more difficult if the nMOS-pMOS process corners are skewed (for example, fast-slow or slow-fast).
The provision of a weak transistor 42 for the pull-up feedback path is typically accomplished by keeping the W/L ratio of transistor 42 as small as possible. This raises a number of problems. First, it is difficult to ensure a weaker pull-up path than pull-down path across all PVT corners simply by sizing transistor 42. Second, if the W/L ratio of transistor 42 is too small, there is a corresponding increase in level shifting delay and current consumption. Third, it is noted that the pull-down path is formed by high-voltage MOSFETs responding to a low voltage domain signal IN/INB while the pull-up path is formed by a high voltage MOSFET responding to a high voltage domain signal OUTDIFFB. The difference in voltage level of the gate control signals inherently weakens the pull-down path as compared to the pull-up path.
To address the third problem, those skilled in the art have designed level shifting circuits of the type shown in FIG. 1 using low voltage input MOSFETS for the n-channel transistors 26 and 28 in the pull-down path in an effort to make the pull-down path stronger. This solution is not satisfactory because it is difficult to limit voltages at the operating terminals of low voltage MOSFETs to within their operating range during normal functioning and during power-up and power-down.
In another solution, a voltage divider is provided at the gate terminal of transistor 42 to attenuate the feedback control signal DIFFOUTB and try to weaken the pull-up path. This solution, however, cannot ensure correct functionality across all PVT corners.
In yet another solution, special devices such as zero/low threshold voltage MOSFETs have been used for transistors 26 and 28 of the pull-down path. This solution, however, requires special process/fabrication steps, such as the use of extra masks or special layout requirements which are not viable for certain designs and which are ineffective from an area and/or cost perspective.
A need thus exists in the art for an improved level shifting circuit.